Point-of-load DC-DC converters for present and future generations of ICs for communication systems and microprocessors must have challenging specifications that include low output voltage and high output current with tight regulation, very small ripple under both steady-state and transient conditions, high power and current densities and high efficiency. All these requirements must be achieved at a very low output voltage that is expected to drop below 1V in the next few years, below 0.6V by year 2010, and below 0.4V by year 2016. Since these devices are required to draw high current, that may exceed 100 A in the future, the power demand will increase dramatically. Therefore, DC-DC converter topologies with higher input voltages may be preferred over those having lower input voltages.
Most of today's non-isolated low-voltage, high-current DC-DC converters are buck derived. Today's isolated DC-DC converters for higher input voltages include symmetrical and asymmetrical half-bridge, full-bridge, active clamped forward, flyback forward and push-pull. The secondary side of the isolated DC-DC converter topology can have different topologies such as forward, center-tapped, or current-doubler.
As the required output voltages become smaller and the input voltages become larger, the required voltage step-down ratio becomes larger, which means larger isolation transformer turns ratio in isolated converters or smaller switching duty cycles in non-isolated converters. Smaller duty switching cycles result in a higher input peak current (higher input rms current) and a larger asymmetric transient response. Moreover, lower output voltage converters must have tight regulation, which requires lower output current and voltage ripple.
As the required output current increases, the isolation transformer secondary winding current becomes larger which increases the winding losses and results in thermal problems that may block the ability to reduce the transformer size required to achieve higher density.
The current-doubler topology is preferred for the secondary side in many power converter applications owing to its advantages including current ripple cancellation, higher current capability, doubled output current and voltage ripple frequency compared to its switches switching frequency, and lower rectification and conduction losses. FIG. 1A shows a conventional prior art current-doubler (CCD) topology 100 that can be used as the secondary side in a DC-DC converter, such as DC-DC converter 600 (FIG. 6A). CCD topology 100 is coupled across a secondary winding 607 (FIG. 6A) of a transformer T1 (FIG. 6A) at nodes A, B. A rectifier, shown as diode D2, has a cathode coupled to one side of the secondary winding 607 of the transformer T1 at node A and to one side of a first inductor L1. A second rectifier, shown as diode D2, has a cathode coupled to the other side of the secondary winding 607 of the transformer T1 at node B and to one side of a second inductor L2. The other sides of inductors L1, L2 are coupled together and to one side of an output 104 (Ro represents the load at output 104). A filter capacitor Co is coupled across output 104. The other side of output 104 is coupled to the anodes of diodes D1 and D2. FIG. 1B shows the key waveforms for a DC-DC converter, such as DC-DC converter 600 (FIG. 6A), having conventional current-doubler topology 100. While the rectifiers shown as diodes D1, D2 can be diodes, it should be understood that rectifiers other than diodes can be used, such as synchronous rectifiers.
However, there are other characteristics that are preferred for the current-doubler when it is used in low output voltage, high output current DC-DC converters with higher input voltages. These include lower output current ripple without increasing the switching frequency much to achieve lower output voltage ripple with the smallest output capacitance, lower output voltage without decreasing the duty cycle or increasing the isolation transformer turns ratio (larger step down capability), lower input current, and that it can be designed to achieve symmetric transient response at both step-up and step-down transients. The latter is preferred in the Adaptive Voltage Positioning (AVP) technique used to reduce the output capacitance required for certain transient maximum output voltage deviation.